Scalable microelectronic package using conductive risers

ABSTRACT

This invention relates to an apparatus and methods for increasing the microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.

FIELD OF THE INVENTION

[0001] The present invention relates to microelectronic packaging, andmore particularly to stacking microelectronic packages in an array toincrease packaging density.

BACKGROUND OF INVENTION

[0002] Trends in microelectronic devices are toward increasingminiaturization, circuit density, operating speeds and switching rates.These trends have directly impacted the complexity associated with thedesign and manufacture of microelectronic dice, microelectronic devices,which include the microelectronic die and a substrate, microelectronicpackages, as well as computing devices in general. Examples of computingdevices include, but are not limited to servers, personal computers and“special” purpose computing devices. Personal computers may have formfactors, such as desktop, laptop, tablet, and the like. “Special”purpose computing devices may include set top boxes, personal digitalassistants, wireless phones, and the like.

[0003] In particular, attention has increasingly shifted tomicroelectronic packaging as a means to meet the demands for enhancedsystem performance. As shown in FIG. 4, current microelectronic packagestypically consist of a microelectronic die 50 electricallyinterconnected to a carrier substrate 52, which are commonlyencapsulated with an encapsulation material 54, such as molded plastic,epoxy or other suitable materials. Additional components, including butnot limited to a heat dissipation device, may be included as part of themicroelectronic package.

[0004] As demand increases, it has become necessary to use multiple dicethat work in conjunction with one another. When using multiple dice,however, it becomes critical to position the dice close together sinceexcessive signal transmission distance deteriorates signal integrity andpropagation times. The use of conventional single-die microelectronicpackages, however, is not commensurate with the need to shorten signaltransmission distance because they typically have an area (or footprint)many times larger than the area of the die. This not only increasestransmission distances, but it also decreases packaging density.

[0005] One solution to create higher density packaging, reduce arearequirements and shorten signal transmission distances has been tovertically stack and electrically interconnect multiple dice in a singlemicroelectronic package. Another solution has been to stack multiplemicroelectronic packages, such as ball grid arrays (BGA) and chip scalepackages (CSP) in an array. Although these stacked microelectronicpackages provide certain advantages, further size reduction andperformance enhancement has been difficult to obtain due to the physicaldimension, design and manufacturing constraints of the individualmicroelectronic packages and the interconnection to the othermicroelectronic packages in the array.

[0006]FIG. 5 shows one assembly known in the art wherein multiplesingle-die microelectronic packages, as shown and described in FIG. 4are stacked in an array. Each carrier substrate 52 has multipleconductive land pads 56 at the die side 60 of the carrier substrate 52that are electrically interconnected to conductive traces (not shown)within the carrier substrate 52. Land pads 56 include but are notlimited to conductive pads, through holes, vias, and any other structureadapted for electrical interconnection. When stacked, the land pads 56are positioned for electrical communication with respective bond pads56′ on the non-die side 62 of carrier substrate 52 of the adjacentmicroelectronic package. An interconnect 58, such as solder, is used toelectrically interconnect the land pads 56 of one microelectronicpackage to the bond pads 56′ of another microelectronic package.

[0007] A number of problems exist with stacking prior artmicroelectronic packages. One, it limits package-to-package interconnectscalability, which involves varying the interconnect pitch (distancebetween center points of the conductive pads) without changing the gapin between packages. For a fine pitch interconnect, the conductiveinterconnect 58 must be decreased so as not to bridge with adjacentinterconnects. However, it is important to keep appropriate standoffdistance from one microelectronic package to another in order toaccommodate the die, encapsulation material, and other components, ifused. To maintain this standoff distance, the interconnect 58 must be ofa sufficient quantity, which limits decreasing the pitch. Decreasing thepitch, however is necessary to keep. up with the advancements inmicroelectronic packages, as more input/output signal leads and powerleads are required.

[0008] Another problem with stacking microelectronic packages is thatthe package carrier substrate 52, especially the carrier substrate atthe bottom of the stack, commonly is subjected to increased stress andflexing. The flexing of the carrier substrate is undesirable because ittends to result in open connections, reduces the microelectronic packageeffectiveness, and leads to microelectronic package failure.

BRIEF DESCRIPTION OF DRAWINGS

[0009]FIG. 1 is a side cross-sectional view of an array ofmicroelectronic packages in accordance with one embodiment of thepresent invention;

[0010]FIG. 2 is a side cross-sectional view of an array ofmicroelectronic packages in accordance with another embodiment of thepresent invention;

[0011]FIGS. 3A-3C are side cross-sectional views showing a process formanufacturing a microelectronic package in accordance with oneembodiment of the present invention;

[0012]FIG. 4 is a side cross sectional view of a known singe-diemicroelectronic package;

[0013]FIG. 5 is a side cross sectional view of a known array ofmicroelectronic packages; and

[0014]FIG. 6 is an example system suitable for practicing the presentinvention in accordance with one embodiment.

DESCRIPTION

[0015] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof wherein like numeralsdesignate like parts throughout, and in which is shown by way ofillustration specific embodiments in which the invention may bepracticed. It is to be understood that other embodiments may be utilizedand structural or logical changes may be made without departing from thescope of the present invention. Therefore, the following detaileddescription is not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims and theirequivalents.

[0016]FIG. 1 is a side cross sectional view of an array of amicroelectronic packages in accordance with an embodiment of the presentinvention. First microelectronic package 8 comprises a microelectronicdie 10 electrically interconnected with a carrier substrate 12. Die 10is encased in an encapsulation material 14, a common practice in theart. It can be appreciated by one skilled in the art, however, thatencapsulation material 14 is provided for a particular purpose, and inother embodiments is not required or provided (i.e. optional). Suitableencapsulation materials include, but are not limited to, molded plastic,resins and epoxies.

[0017] Carrier substrate 12 of first microelectronic package 8 has landpads 16 exposed at a die side 9 of carrier substrate 12, outside theperiphery of the die 10 and encapsulation material 14. It is understoodin the art that land pads is a term for referring to pads, platedthrough holes, or any other structure that allows for electricalcommunication between the carrier substrate circuitry and an attachedcomponent.

[0018] Intermediate substrate 20 can be coupled or laminated to thecarrier substrate 12, such that it encompasses the periphery of die 10and encapsulation material 14. Intermediate substrate 20 comprises avariety of dielectric materials, including but not limited to C-stagethermoset polymer resins, epoxies, and the like. In other embodimentsthat do not include encapsulation material 14, the intermediatesubstrate 20 can encompass the periphery of die 10, or it may have acavity that is sized to accommodate the die volume such that it coversdie 10.

[0019] Intermediate substrate 20 has a plurality of conductive risers 18disposed therein. Conductive risers 18 have a first end 13 and a secondend 15, and are in relative alignment such that the first end 13 may bein electrical communication with land pads 16 of carrier substrate 12.The second end 15 of conductive risers 18 are also positioned to enableelectrical interconnection with bond pads 16′ of adjacent secondmicroelectronic package 7. Conductive risers 18 may reduce the size ofinterconnects 22 needed for electrical interconnection, which may allowfor a finer pitch in land pads 16 and bond pads 16′. Conductive risers18 comprise a variety of conductive materials, including, but notlimited to, copper, gold, nickel, and various other metals and metalalloys.

[0020] Second microelectronic package 7 can be positioned adjacent tomicroelectronic package 8. Microelectronic package 7 is substantiallythe same as first microelectronic package 8, and comprises amicroelectronic die 10 encased in encapsulation material 14 that iselectrically interconnected to a carrier substrate 12. Carrier substrate12 of second microelectronic package 7 further comprises land pads 16 onthe die side 9 and bond pads 16′ on the non-die side 11. It isunderstood in the art that bond pads is a term for referring to pads,plated through holes, or any other structure that allows for electricalcommunication between the carrier substrate circuitry and an attachedcomponent.

[0021] Bond pads 16′ are positioned for relative alignment andelectrical interconnection with the second end 15 of conductive risers18 disposed in the intermediate substrate 20 of the firstmicroelectronic package 8. Interconnects 22 electrically interconnectconductive risers 18 with bond pads 16′. Interconnects 22 comprise aconductive material including, but not limited to, leaded solder,lead-free solder, conductive or conductor-filled epoxy, and otherconductive substances known to those skilled in the art. Secondmicroelectronic package 7 also comprises intermediate substrate 20,having conductive risers 18 disposed therein, in much the same way asdiscussed above with regard to the intermediate substrate 20 for firstmicroelectronic package 8.

[0022] Third microelectronic package 6 may be positioned adjacent tosecond microelectronic package 7. Microelectronic package 6 also issubstantially the same as first microelectronic package 8, and comprisesa microelectronic die 10 encased in encapsulation material 14 that iselectrically interconnected to a carrier substrate 12. Carrier substrate12 of third microelectronic package 6 comprises bond pads 16′ on thenon-die side 11 of carrier substrate 12. Bond pads 16′ of thirdmicroelectronic package 6 are positioned for relative alignment andelectrical interconnection with the conductive risers 18 of theintermediate substrate 20 of second microelectronic package 7.Interconnects 22 electrically interconnect conductive risers 18 withbond pads 16′ of the third microelectronic package 6.

[0023] In addition to the stacked array of three microelectronicpackages 8,7,6, as illustrated in FIG. 1, other embodiments of stackedarrays in accordance with the present invention may have more or fewermicroelectronic packages in the array. Also, intermediate substrate 20can be secured to carrier substrate 12 such that it may act as astiffener to increase the rigidity of a microelectronic package, whichhelps prevent flex in the intermediate substrate 20, thereby reducingthe potential for open circuits leading to flex-induced interconnectfailure. This can reduce the manufacturing costs of microelectronicpackages, where in the past, the use of various stiffeners to preventcarrier substrate flex was required. Additionally, the use of theconductive risers 18 may also allow for fine pitch package-to-packageinterconnection scalability because the height required to clear theadjacent microelectronic package is no longer constrained byinterconnects 22, but rather may be dependent on the height and width ofthe conductive risers 18.

[0024]FIG. 2 is a side cross sectional view of an array ofmicroelectronic packages in accordance with an embodiment of the presentinvention. The stacked array comprises multiple microelectronic packageseach having one or more stacked microelectronic dice. Firstmicroelectronic package 8′ has many of the same elements as firstmicroelectronic package 8 as described with respect to FIG. 1. Theconductive risers 18′ of first microelectronic package 8′, however, areslightly elongated in order to accommodate increased package heightcaused by the additional microelectronic dice 10. The conductive risers18′ may help to maintain the package to package scalability withoutincreasing the pitch of the land pads 16 or bond pads 16′. Likewise, theconductive risers 18 of second microelectronic package 7′ can be adaptedto provide a predetermined standoff height for the third microelectronicpackage 6′, again without affecting package to package scalability.

[0025] The gap height 17 between microelectronic packages may beadjusted for a variety of reasons, including but not limited to themicroelectronic package thickness. Adjustment to the gap height may helpaccommodate additional components such as heat spreaders (not shown),provide a required standoff distance, or increase the pitch of themicroelectronic packages without increasing the interconnect 22.

[0026]FIGS. 3A-3C are side cross-sectional views of a method offabricating a microelectronic package adapted for use in a stacked arrayin accordance with an embodiment of the present invention. FIG. 3Aillustrates an intermediate substrate blank 30 of a predetermined sizethat has a first side 46 and a second side 48. Adhesive layer 32 can beapplied to the second side 48 of intermediate substrate blank 30.Intermediate substrate blank 30 can be made out of variety of dielectricmaterials. As previously discussed with regard to intermediate substrate20 in FIG. 1, one example is the use of a C-stage thermoset polymerresin for intermediate substrate 30 and a B-stage thermoset polymerresin for adhesive layer 32. Use of C-stage and B-stage resins are knownin the are; and can be done in a variety of ways.

[0027] The substrate blank material may be application dependent, suchas to provide a predetermined material stiffness, and/or control thecoefficient of thermal expansion (CTE). Thus, other suitable dielectricmaterials for intermediate substrate blank 30 may include, but are notlimited to polymer matrix composites, such as glass cloth reinforcedpolymer.

[0028]FIG. 3B is a cross sectional view of the manufacturing process,where the conductive riser 18 may be inserted into an accommodatingaperture 35 in substrate blank 30, in accordance with one embodiment.Conductive material 34, having a predetermined thickness, comprises aconductive plating 36 applied to the first end 40 and second end 42 ofconductive material 34. Conductive plating 36 enables electricalinterconnection with land pads 16 of carrier substrate 12 (shown in FIG.3C) and bond pads 16′ (not shown) of an adjacent microelectronicpackage. Suitable materials for conductive plating 36 include, but arenot limited to, electrolytic tin plating and lead or lead-free solder.

[0029] Conductive riser 18 can be removed from conductive material 34using, for example, a punch and die process. Aperture 35 in intermediatesubstrate blank 30 can be formed by a similar process. As conductiveriser 18 is being punched out of conductive material 34, it can beaccordingly pressed into aperture 35. Conductive riser 18 and aperture35 may be created by other techniques, including but not limited to,drilling, augering, laser etching or inserting the conductive material34 into aperture 35 in a non-solid phase and curing to a solid phase.

[0030] It is desirable for the overall thickness of the conductivematerial 34 and the conductive plating 36 to be the same as or greaterthan the thickness of the intermediate substrate blank 30′, includingadhesive layer 32, such that a portion of the conductive plating 36 isflush with or protrudes slightly above and below the surfaces of theintermediate substrate blank 30 and adhesive layer 32, when inserted inaperture 35. A slight protrusion allows the conductive riser 18 toelectrically interconnect with land pads 16 and bond pads 16′ (notshown) when the intermediate substrate 30 is secured to themicroelectronic package carrier substrate 12, for example, during thehot press process, or during a reflow process. In other embodiments,conductive risers 18 are formed from a conductive material 34 withoutconductive plating 36. Conductive plating can be pre-positioned on theland pads 16 and bond pads 16′ such that electrical interconnection ismade during a reflow process or the hot press process.

[0031]FIG. 3C is a cross-sectional view of an intermediate substratefabrication process in accordance with an embodiment of the presentinvention. Second aperture 38 may be formed in intermediate substrateblank 30, which in turn may form the intermediate substrate 31. Secondaperture 38 enables intermediate substrate 31 to over lay carriersubstrate 12, accommodating the size and shape of the microelectronicdie 10 and, optionally encapsulation material 14. Intermediate substrate31 may be placed the die side 44 of carrier substrate 12 ofmicroelectronic package 33, such that the conductive plating 36 of the.conductive risers 18 are in electrical communication with correspondingland pads 16. As previously discussed, in another embodiment conductiveplating 36 can be pre-positioned on land pad 16 and not on conductiveriser 18.

[0032] Intermediate substrate 31 may be coupled to microelectronicpackage 33 by using a suitable processes, depending on the material usedfor adhesive layer 32. In one embodiment wherein the adhesive layer 32is a B-stage resin, a hot press process may be used to secureintermediate substrate 31 to carrier substrate 12. The hot press processmay help to ensure an electrical/mechanical bond between land pads 16and conductive risers 18 by causing conductive plating 36 to flow andcure.

[0033] In one embodiment, using a C-Stage resin for intermediatesubstrate blank 30 and a B-stage resin for adhesive layer 32, a vacuumcan be applied such that the pressure within the chamber is less thanabout 10 kilo Pascals. Heat and pressure can then be applied to bondcarrier substrate 12 and intermediate substrate 31, as well aselectrically/mechanically bond land pads 16 to the correspondingconductive risers 18. Applying a pressure about between 0.5-10 megaPascals at a temperature about between 150-350 degrees Celsius mayprovide acceptable lamination of the intermediate substrate 31 tocarrier substrate 12, and accordingly may act as a package stiffener.Further, this may help to ensure electrical interconnection between landpads 16 and conductive risers 18. It can be appreciated that thepressure and temperature of the hot press may be varied depending on thecuring properties of adhesive layer 32 and, if used, the conductiveplating 36.

[0034]FIG. 6 is an example system suitable for practicing one embodimentof the present invention. A microelectronic package array 92 of thepresent invention is coupled to system board 90 through high speed bus96. System board 90 may be a carrier substrate, such as a motherboard orother printed circuit boards. As shown, the system board 90 alsoincludes a memory 94 configured to store data, coupled to the systemboard 90 through high speed bus 96. Memory 94 may include but is notlimited to dynamic random access memory (DRAM), synchronous DRAM(SDRAM), and the like. In the embodiment shown, an active coolingmechanism 98 is coupled to the microelectronic package array 92 to helpkeep the microelectronic package 92 from overheating. Active coolingmechanism may include, but is not limited to fans, blowers, liquidcooling loops and the like.

[0035] Although specific embodiments have been illustrated and describedherein for purposes of description of the preferred embodiment, it willbe appreciated by those of ordinary skill in the art that a wide varietyof alternate and/or equivalent implementations calculated to achieve thesame purposes may be substituted for the specific embodiment shown anddescribed without departing from the scope of the present invention.Those with skill in the art will readily appreciate that the presentinvention may be implemented in a very wide variety of embodiments. Thisapplication is intended to cover any adaptations or variations of theembodiments discussed herein. Therefore, it is manifestly intended thatthis invention be limited only by the claims and the equivalents thereof

1. A microelectronic package, comprising: a carrier substrate, thecarrier substrate having a die side and a non-die side, the die sidehaving a first area for [a die] electrically interconnecting a die tothe die side of the carrier substrate, and a second area having one ormore land pads on the die side of the carrier substrate, the one or moreland pads having a predetermined pitch; and an intermediate substratedirectly coupled to the die side of the carrier substrate, theintermediate substrate having one or more conductive risers disposedtherein corresponding to the one or more land pads, the one or moreconductive risers configured to cooperate with the corresponding landpads to provide a standoff distance sufficient to accommodate the die,and each of the one or more conductive risers having a first end and asecond end, the first end being electrically interconnected to the landpad.
 2. The microelectronic package of claim 1, wherein the conductiveriser comprises substantially oxygen-free copper.
 3. The microelectronicpackage of claim 1, further comprising a conductive plating on the firstend of the conductive riser.
 4. The microelectronic package of claim 3,wherein the conductive plating is selected from a group including leadedsolder, lead-free solder and tin.
 5. The microelectronic package ofclaim 1, wherein the intermediate substrate is laminated to the die sideof the carrier substrate of the microelectronic package.
 6. Amicroelectronic package array, comprising: a first microelectronicpackage having a first carrier substrate, the first carrier substratehaving a die side and a non-die side, the die side having a first areafor electrically interconnecting a die to the die side of the carriersubstrate, and a second area having one or more land pads on the dieside of the carrier substrate, the one or more land pads having apredetermined pitch; an intermediate substrate directly coupled to thedie side of the carrier substrate, the intermediate substrate having oneor more conductive risers disposed therein corresponding to the one ormore land pads, the one or more conductive risers configured to create astandoff distance sufficient to accommodate the first die and one ormore additional components without affecting the predetermined pitch,and each of the one or more conductive risers having a first end and asecond end, the first end being electrically interconnected to the landpad; and a second microelectronic package having a second carriersubstrate, the second carrier substrate having a die side and a non-dieside, the die side having a first area for electrically interconnectinga die to the die side of the second carrier substrate, and a second areahaving one or more bond pads on the non-die side, the one or more bondpads being electrically interconnected to the second end of the one ormore conductive risers.
 7. The microelectronic package array of claim 6,wherein the a conductive riser comprises oxygen-free copper.
 8. Themicroelectronic package array of claim 6, further comprising aconductive plating on the first end of the conductive riser.
 9. Themicroelectronic package of claim 8, wherein the conductive plating isselected from a group including leaded solder, lead-free solder and tin.10. The microelectronic package array of claim 6, further comprising aninterconnect electrically coupling the bond pad to the second end of thecorresponding conductive riser of the first microelectronic package. 11.The microelectronic package array of claim 10, wherein the interconnectis lead free solder.
 12. The microelectronic package array of claim 6,wherein the intermediate substrate is laminated to the die side of thefirst carrier substrate of the first microelectronic package.
 13. Asystem, comprising: a system board; a bus coupled to the system board tofacilitate data exchange; a memory configured to store data, the memorycoupled to the system board through the bus; a microelectronic packagearray coupled to the system board through the bus, the microelectronicpackage array comprising a first microelectronic package having a firstcarrier substrate, the first carrier substrate having a die side and anon-die side, a first die electrically interconnected to the die side ofthe first carrier substrate, and a land pad on the die side of the firstcarrier substrate, an intermediate substrate coupled to the die side ofthe first carrier substrate, the intermediate substrate having aconductive riser disposed therein, the conductive riser having a firstend and a second end, the first end being electrically interconnected tothe land pad, a second microelectronic package having a second carriersubstrate, the second carrier substrate having a die side and a non-dieside, a second die electrically interconnected to the die side of thesecond carrier substrate, and a bond pad on the non-die side, the bondpad being electrically interconnected to the second end of theconductive riser; and an active cooling device coupled to themicroelectronic package array.
 14. The system of claim 13, furthercomprising a conductive plating on the first end of each a conductiveriser.
 15. The system of claim 14, wherein the conductive plating isselected from a group including leaded solder, lead-free solder and tin.16. The system of claim 13, further comprising an interconnectelectrically coupling each bond pads to the second end of eachcorresponding the a conductive riser of the first microelectronicpackage.
 17. The system of claim 13, wherein the intermediate substrateis laminated to the die side of the first carrier substrate of the firstmicroelectronic package.
 18. The system of claim 13, wherein theinterconnect is lead free solder.
 19. A method for fabricating amicroelectronic package array, comprising: providing a firstmicroelectronic package having a first carrier substrate, the firstcarrier substrate having a die side and a non-die side, a dieelectrically interconnected to the die side of the first carriersubstrate, and a plurality of land pads on the die side of the firstcarrier substrate; providing an intermediate substrate having aplurality of conductive risers disposed therein, the intermediatesubstrate adapted to overlay the first carrier substrate such that eachof the plurality of conductive risers correspond to one of the pluralityof land pads; placing the intermediate substrate on the die side of thefirst carrier substrate; electrically interconnecting the plurality ofconductive risers with the corresponding land pads; providing a secondmicroelectronic package having a second carrier substrate, the secondcarrier substrate having a die side and a non die side, a dieelectrically interconnected to the die side of the second carriersubstrate, and a plurality of bond pads the non die side of the secondcarrier substrate, each of the plurality of bond pads correspond to oneof the plurality of conductive risers; placing the non die side of thesecond microelectronic package adjacent to the intermediate substrate;and electrically interconnecting the plurality of bond pads to theplurality of conductive risers.
 20. The method of claim 19, whereinproviding the intermediate substrate having a plurality of conductiverisers disposed therein includes providing a plurality of conductiverisers having a height adapted to position the non die side of thesecond microelectronic package a predetermined distance from the dieside of the first microelectronic package.
 21. The method of claim 19,further comprising increasing the pitch of the land pads and bond pads,and correspondingly increasing the number of the plurality of conductiverisers disposed in the intermediate substrate.
 22. The method of claim19, wherein placing the intermediate substrate on the first side of thefirst carrier substrate further comprises laminating the intermediatesubstrate to the die side of the first carrier substrate using a hotpress process.
 23. A method for manufacturing a microelectronic package,comprising: providing a first carrier substrate having a die side and anon die side, a die electrically interconnected to the die side of thefirst carrier substrate, and a plurality of land pads disposed on thedie side of the first carrier substrate; providing an intermediatesubstrate blank having a first side and a second side; applying anadhesive material the second side of the intermediate substrate blank;forming a plurality of first apertures of a predetermined size in theintermediate substrate blank that extend from the first side to thesecond side; providing a conductive riser material; sizing theconductive riser material to be substantially the same as the pluralityof first apertures, thereby creating a plurality of conductive riserscorresponding to the plurality of first apertures; inserting theplurality of conductive risers into the corresponding plurality of firstapertures; forming a second aperture in the intermediate substrate blankhaving a cross sectional area the same as or larger than the die,thereby creating an intermediate substrate; and placing the intermediatesubstrate on the first carrier substrate such that the die is disposedwithin the second aperture and the plurality of conductive risers areelectrically interconnected with the corresponding plurality of landpads.
 24. The method of claim 23, wherein placing the intermediatesubstrate further comprises laminating the intermediate substrate to thefirst carrier substrate.
 25. The method of claim 24, wherein laminatingthe intermediate substrate to the carrier substrate further comprises:placing the microelectronic package in a vacuum chamber; creating avacuum in the vacuum chamber; applying heat to the intermediatesubstrate and the first carrier substrate; applying pressure to theintermediate substrate and the first carrier substrate; releasing thepressure; and cooling the microelectronic package.
 26. The method ofclaim 25, wherein creating a vacuum further comprises creating apressure of about less than ten kilo Pascals.
 27. The method of claim25, wherein applying heat further comprises raising the temperature toabout between 150° C. and 350° C.
 28. The method of claim 25, whereinapplying a pressure further comprises increasing the pressure to a rangebetween 0.5 mega Pascals and 10 mega Pascals.
 29. A microelectronicpackage, comprising: a carrier substrate, the carrier substrate having adie side and a non-die side, and a plurality of land pads disposed onthe die side of the carrier substrate, the land pads having apredetermined pitch; a die electrically interconnected to the die sideof the carrier substrate; and an intermediate substrate coupled to thedie side of the carrier substrate, the intermediate substrate having aplurality of conductive risers disposed therein, the conductive risersadapted to cooperate with the land pads to provide a clearance heightsufficient to accommodate the die and at least one other component. 30.The microelectronic package of claim 29, wherein the at least one othercomponent is selected from a group consisting of heat spreaders, activecooling devices, encapsulates, and additional dice.